1. Field of the Invention
The present invention relates to analogue to digital (A/D) conversion devices equipped with a plurality of delay units arranged in multiple stages, and each of the delay units is capable of delaying a received pulse signal by a delay time which corresponds to an input voltage.
2. Description of the Related Art
There have been used various types of analogue to digital (A/D) conversion devices having a conventional structure. For example, a patent document, Japanese patent laid open publication No. H05-259907 has disclosed a conventional A/D conversion device equipped with a pulse delay circuit. The pulse delay circuit is comprised of a plurality of delay units. The delay units are arranged in a ring loop shape. Each of the delay units delays a received pulse signal by a corresponding delay time determined by a magnitude of an input voltage. The conventional A/D conversion device receiveds analogue input signals and converts the received analog input signal to digital output signals. The digital output signals represent numeric data.
In the conventional A/D conversion device disclosed in Japanese patent laid open publication No. H05-259907, an activation signal having an activation level (for example, a high level) is generated in order to initiate the operation of the pulse delay circuit. After this, an output signal of each of the delay units and a counter output signal of a pulse loop counter are latched at a timing of a sampling signal. The pulse loop counter is capable of counting a number of loops of pulse signals circulated in the pulse delay circuit. In the conventional A/D conversion device, the latched signals are encoded in binary digits which represent the number of the delay units through which the pulse signals have passed. The conventional A/D conversion device outputs the encoded signals as A/D conversion data. Because the activation signal and the sampling signal are generated at a constant period, the conventional A/D conversion device outputs the A/D conversion data items at constant time intervals.
There is a conventional technique to perform the A/D conversion device previously described at a high speed. The conventional technique always maintains the activation signal having the activation level, and encodes the number of the delay units, through which the pulse signals have passed, in binary digits during one period of the sampling signal. In this conventional structure, the pulse delay circuit and the pulse loop counter must obtain A/D conversion data on the basis of a difference between two successive encoded data items because the operation of the pulse delay circuit and the operation of the pulse loop counter are not reset in every A/D conversion operation.
However, because the conventional technique previously described requires an additional subtraction unit, it becomes difficult for the subtraction unit to follow and adapt a period of receiving A/D conversion data when the operation of the A/D conversion device operates at a high speed (for example, at a GHz speed). This introduces that the A/D conversion device having the conventional structure does not perform a correct A/D conversion operation.
Further, in the conventional technique of continuously performing the operation of the pulse delay circuit and the pulse loop counter without any resetting process, because the period of the sampling signal and the period of counting the number of the delay units through which the pulse signals have passed have the same value, it is difficult to detect a high frequency component, which is higher than a frequency of the sampling frequency, to the A/D conversion data.